Professionals are invited to submit proposals for Special Sessions. Special Sessions should focus on a topic which is of particular interest to the FDL audience. Special Sessions consist of two to four invited talks. Speakers are requested to either submit a one page abstract of their presentation, or to submit a short or full paper that goes through the regular review and publication process. Potential organizers of a Special Session must submit a brief proposal (no more than two pages) which describes the topic, the intended audience, as well as a list of possible speakers to fdl2019@easychair.org
Important Deadlines
- Special Sessions: March 22, 2019
- Abstract Deadline: April 19, 2019 May 03, 2019
- Paper Deadline: April 26, 2019 May 10, 2019
- Author Notification: June 21, 2019 June 28, 2019
- Final Version: July 19, 2019
Heinz Riener
EPFL, Lausanne, CH
Abstract:
Design understanding is the problem of gaining knowledge from an unknown system implementation. The problem arises frequently in practice and has numerous application, e.g., in debugging, reverse engineering, automatic documentation, security analysis, specification mining, or assertion-based verification. An algorithmic solution to design understanding, which derives knowledge from an unknown system implementation automatically, has a potential of simplifying many time-consuming engineering tasks, leading to an improved productivity of design teams, and a reduction of development cost. The inherent complexity of today's implementations make algorithmic design understanding challenging. This special session brings together researchers from the field of design understanding, property generation, and natural language processing. Its topic focuses on the automatic generation of formal properties in temporal logic. Temporal logics extend Boolean logic by temporal operators and path quantifiers and are widely used as specification language for digital hardware. Using formal properties to specify a hardware design has undeniable benefits: a fixed, formal semantics of the statements and formal proofs that these statements indeed hold. However, when formal properties are used to describe the intended behavior of a hardware design, it is often difficult to write specifications that accurately reflect the intent of the designer. In the special session, recent advancements in the field of design understanding are discussed, which can be used to aid human designers to generate formal properties more effectively.
Daniel Große
University of Bremen/DFKI Bremen, DE
Abstract:
RISC-V is an open and free Instruction Set Architecture (ISA). Since 2015, the RISC-V ISA standard is maintained by the non-profit RISC-V foundation that has more than 200 members aiming innovation. For IoT processors RISC-V is a game changer, and meanwhile big companies start to adopt RISC-V and contribute to its ecosystem. An important design factor today is the control and adaptivity of a system with respect to non-functional properties, like for example application-specific timing and power budgets. On the rise are automated firmware-based methodologies. This special session focusses particularly on the generation, verification and optimization of firmware running on RISC-V based systems. With the focus on the application scenario, new methods are required for early, efficient and systematic firmware design taking the underlying hardware architecture into account
FDL 2019 - Southampton, United Kingdom
Contact: General chair
Tom J Kazmierski tjk@ecs.soton.ac.uk
Contact: Program chairs
Reinhard von Hanxleden rvh@informatik.uni-kiel.de
Terrence Mak tmak@ecs.soton.ac.uk
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