FDL 2017

Forum on specification & Design Languages




@Verona, Italy
September 18-20, 2017



@Verona, Italy





Keynotes




Roberto Zafalon
STMicroelectronics

1st Keynote: IoT trends and innovatve applications

Abstract:
The keynote will tackle with the three major IoT challenges today: interoperability, security, and business model (monetization). The strong enabling technologies roots (i.e. semiconductor and IP Design) will set the stage for a comprehensive view of the key IoT end-markets and of the most innovative applications expected to boost the massive deployment of IoT by the next 4 years.

Bio:
Dr. Roberto Zafalon is EU Technology Programmes Director - Italy, in charge to foster and leverage the link between ST technology groups and the R&D cooperative EU programs. at STMicroelectronics, Agrate Brianza (Milano), Italy. In his current capacity since July 2007, he elaborates the vision and roadmap, seeks for project financing and drives industrial R&D teams to pursue innovative solutions in the field of embedded systems and nanoelectronics, for corporate product divisions and labs. He is with STMicroelectronics (one of world’s top 5 semiconductor firms) since 25 years. He is Steering Board member of ARTEMIS-IA and EPOSS (the European Technology Platform on Smart Systems Integration) and member of AENEAS working groups. He currently is, and has been in the past, General Project Manager and Coordinator of major Integrated Projects under FP6, FP7 and JTI calls 2009-2013, including KET Pilot Lines. He has been selected by FP7-ICT and ARTEMIS JU as independent expert to review the project submitted to some past calls. From 2000 until June 2007, he has been the head of the Competence Center for Low Power System Design at the Advanced System Technology, the ST’s Corporate System R&D group. The main targets have been the next generation's embedded systems trade-offs, including algorithmic and architectural design exploration and power optimization, SW/HW partitioning and RF optimization and co-verification, power profiling, estimation and macro-modeling, energy efficient Network on Chip and RT-OS featuring dynamic power management policies. As far as the on-chip communication is concerned, shared bus interconnects represent only a partial, short-term solution, because of their limited scalability. We focus on parallel and scalable interconnect architectures to support the rapidly growing communication bandwidth’s requirement, both in terms of Low Power Multi Processor Platforms and Energy Efficient NoC’s.

- Web page: https://it.linkedin.com/in/roberto-zafalon-7aaa129





Jan Kuper
QBayLogic

2nd Keynote: Programming in a Heterogeneous World

Abstract:
This talk will argue that translation mechanisms from well known and well developed programming methodologies into low-level platform specific programming is doomed to fail because the way each type of computing platform deals with its internal space and time in a different way. Instead, we will argue that we should start from a really platform independent level, for which mathematics is a good candidate.

Bio:
Jan Kuper has a PhD from the University of Twente in the field of mathematics, and is the original founder of the CλaSH project. He is a senior staff member of the Computer Architecture group at the University of Twente. Jan is the lecturer of the highly appreciated functional programming course at the University of Twente. Although this is an elective course, it is followed by nearly 100% of the computer science students based on the recommendations of other students; all in large part due to Jan's engaging teaching practices.

- Web page: https://www.linkedin.com/in/jan-kuper-15bab311



Sandeep Shukla
IIT Kanpur

3rd Keynote: Cyber Security of cyber physical critical infrastructure

Abstract:
In this talk we will explore this question, and we will show that there is indeed benefit in taking approaches based on formalized languages for system specification, or system design, not only for analyzability at various abstraction levels of risk, and visibility of attack vectors but also for better comprehension of systemic risks, guiding resilient design of system architecture, and budgeting resources in optimal manner.

Bio:
Sandeep Kumar Shukla is currently Poonam and Prabhu Goel Chair Professor and Head of Computer Science and Engineering Department, Indian Institute of Technology, Kanpur, India. He is currently the Editor-in-Chief of ACM Transactions on Embedded Systems, and associate editor for ACM transactions on Cyber Physical Systems. Professor Sandeep K. Shukla is an IEEE fellow, an ACM Distinguished Scientist, and served as an IEEE Computer Society Distinguished Visitor during 2008-2012, and as an ACM Distinguished Speaker during 2007-2014. In the past, he has been associate editors for IEEE Transactions on Computers, IEEE Transactions on Industrial Informatics, IEEE Design & Test, IEEE Embedded Systems Letters, and many other journals. He was a faculty at the Virginia Tech, Arlington, Virginia between 2002 and 2015. In 2014, he was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE)[1] for contributions to applied probablistic model checking for system design. He has authored several books on systems

- Web page: https://www.cse.iitk.ac.in/users/sandeeps/





Tutorials



  • HIFSuite for Cyber-physical VPs generation
  • The SPARK 2014 programming language




Technical Program








Social Program



  • Welcome Reception
  • Social Event
    • On Tuesday, September 19th at 8:30 p.m., all partipants are invited to Re Teodorico restaurant. While having a beautiful view of Verona by night, we will serve a dinner and we invite everyone to have a nice summer evening with us. During this, contacts to other partipants can be strengthened and the day is concluded in a relaxed atmosphere. The social event will start at 6:30 p.m. (Piazza Brà). We collect all attendees at the “Accademia“ for the visit of the best historical sites of Verona. We will then arrive to the funicular of Castel San Pietro, that we will use for reaching the restaurant.






FDL 2017 is in Verona, Italy